AUTO_CMD_EBIT_ERR=Val_0x0, AUTO_CMD_CRC_ERR=Val_0x0, AUTO_CMD_TOUT_ERR=Val_0x0, AUTO_CMD_RESP_ERR=Val_0x0, CMD_NOT_ISSUED_AUTO_CMD12=Val_0x0, AUTO_CMD12_NOT_EXEC=Val_0x0, AUTO_CMD_IDX_ERR=Val_0x0
Auto CMD Status Register
| AUTO_CMD12_NOT_EXEC | Auto CMD12 Not Executed. If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. Setting this bit to 0x1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. If this bit is set to 0x1, error status bits (D04 to D01) is meaningless. This bit is set to 0x0 when Auto CMD Error is generated by Auto CMD23. 0 (Val_0x0): Executed 1 (Val_0x1): Not executed |
| AUTO_CMD_TOUT_ERR | Auto CMD Timeout Error. This bit is set if no response is returned with 64 SD_CLK cycles from the end bit of the command. If this bit is set to 0x1, error status bits (D04 to D01) are meaningless. 0 (Val_0x0): No error 1 (Val_0x1): Time out |
| AUTO_CMD_CRC_ERR | Auto CMD CRC Error. This bit is set when detecting a CRC error in the command response. 0 (Val_0x0): No Error 1 (Val_0x1): CRC Error Generated |
| AUTO_CMD_EBIT_ERR | Auto CMD End Bit Error. This bit is set when detecting that the end bit of command response is 0x0. 0 (Val_0x0): No error 1 (Val_0x1): End bit error generated |
| AUTO_CMD_IDX_ERR | Auto CMD Index Error. This bit is set if the command index error occurs in response to a command. 0 (Val_0x0): No error 1 (Val_0x1): Error |
| AUTO_CMD_RESP_ERR | Auto CMD Response Error. This bit is set when the SDMMC_XFER_MODE_R[RESP_ERR_CHK_ENABLE] bit is set to 0x1 and an error is detected in R1 response of either Auto CMD12 or CMD13. This status is ignored if any bit between D00 to D04 is set to 0x1. 0 (Val_0x0): No error 1 (Val_0x1): Error |
| CMD_NOT_ISSUED_AUTO_CMD12 | Command Not Issued By Auto CMD12 Error. This bit is set to 0x0 when Auto CMD Error is generated by Auto CMD23. 0 (Val_0x0): No error 1 (Val_0x1): Not issued |